1. Field of the Invention
The disclosure relates in general to a semiconductor structure and a manufacturing method of the same, and more particularly to a semiconductor structure and a manufacturing method of the same for logic process.
2. Description of the Related Art
In a typical semiconductor manufacturing process, the active region and the channel width are defined first, which is the shallow trench isolation (STI) process, and then the channel length is defined in the gate electrode manufacturing process. Next, the N−/P− region is defined and formed according to the gate electrode. And then, the gate spacer is formed according to the relief structure of the gate electrode followed by the definition of the N+/P+ region assisted by the gate spacer. Finally, after the interlayer dielectric (ILD) insulating layer is formed, in the following contact formation process, the contacts are formed aiming to the N+/P+ region. In the typical manufacturing process, the formation of STI/gate electrode/contacts has to follow the strictest design rules of the manufacturing process. Therefore, the costs as well as the difficulty of the manufacturing process are relatively high.